The present invention relates to a bit shift detecting circuit for detecting the amount of bit shift of a synchronizing signal included in a synchronizing block and a synchronizing signal detecting circuit using the bit shift detecting circuit.
Nowadays, in a video tape recorder which is what is called a VTR, a digital VTR capable of recording and reproducing an image with higher image quality than that of an analog VTR using a low carrier wave FM recording system has been put into practice with the aid of the development of a digital recording system.
The schematic configuration of the digital VTR is illustrated in FIG. 1.
In a recording system of the digital VTR, an analog video signal to be input is converted into a digital signal by an A/D (analog/digital) converter 51, the digital signal is quantized and the thus quantized digital signal is sent to a digital signal processing circuit 52.
In the digital signal processing circuit 52, the digital video signal is divided for respective blocks having a proper size, and then, the divided digital video signal is subjected to an orthogonal transformation and variable-length coding. The obtained coded signal undergoes shuffling and scrambling processings and an error correcting parity is applied to data. At this time, the parity relative to the vertical data of two-dimensionally arranged data is called an external code and the parity relative to the horizontal data is called an internal code. The processed data in this way is sent to a synchronization/ID adder 53.
In the synchronization/ID adder 53, a synchronizing signal of 2 bytes for detecting synchronization which is what is called a synchronization and an identification code of 3 bytes which is what is called an ID are applied to the sent signal and the signal is supplied to an encoder 54.
In the encoder 54, an encoding processing for an error correction and modification is executed for each frame of the supplied signal and a channel coding is carried out for converting the error-corrected and modified signal into a signal suitable for a high density recording, so that a recording signal is output. The recording signal is recorded on a magnetic tape through a recording head 55.
In the reproducing system, the recording signal on the magnetic tape is read by a reproducing head 56 and the read signal is supplied to a decoder 57. In the decoder 57, the reproduced signal is separated for respective frames and decoded and the decoded signal is supplied to a synchronization detector 58.
In the synchronization detector 58, a synchronization is detected from the sent signal and a data signal is demodulated based on the synchronization. The demodulated data is sent to a digital signal processing circuit 59.
In the digital signal processing circuit 59, the demodulated data is subjected to processings including an error correction, deshuffling and descrambling, and then, the processed data is subjected to a reverse orthogonal transformation so that a processing such as the expansion of data is effected.
The expanded data is converted into an analog signal by a D/A converter 60 and the analog signal is supplied to an external monitor or the like.
Now, a schematic configuration of an example of a synchronizing signal detecting circuit which is what is called a synchronization detecting circuit is shown in FIG. 2, which detects a synchronization for each block of an internal code in the above described synchronization detector 58.
The data of the synchronizing block having a predetermined size obtained by adding the synchronization of 2 bytes and the identification code ID of 3 bytes or the like to the data output from the decoder 57 is input as parallel data of 8 bits to the above mentioned synchronization detecting circuit. The synchronization and the identification code ID of the synchronizing block data previously input are delayed by one synchronizing block in a delay memory 31 and the thus obtained input data is fed to a variable shift register 33. Further, the synchronization and the identification code ID of a synchronizing block input following the above mentioned synchronizing block are sent to the variable shift register 34 and also to a bit shift detector 32.
The parallel data of 8 bits to be input is not always interrupted at the first bit position of a leading synchronization SY of the synchronizing block. The interruption of the synchronizing block, that is, a phase is indeterminate. Therefore, the bit shift detector 32 detects the amount of shift of the first bit position of the synchronization SY of the synchronizing block input subsequently and outputs it as bit shift phase information to the variable shift register 33 and the variable shift register 34 respectively.
Herein, when the pattern of accurate synchronizations SY.sub.0, SY.sub.1 to be supplied to the bit shift detector 32 is, for example, `2E.D 3` in a hexadecimal notation, as shown in FIG. 3A, binary data is represented by `0111010011001011` from LSB (Least Significant Bit) first, that is, the least significant bit of the binary data. The value of `2E, 3D` also serves as a synchronization word to be sent to coincidence detectors 71 and 72. As illustrated in FIG. 3B, for this synchronization word, there are prepared eight kinds of different patterns respectively having 4 bits, which include PHASE 0 having the amount of shift of 0 bit to PHASE 7 having the amount of shift of 7 bits as pre-detect-words.
Accordingly, even if the break of eight bits of the synchronization SY.sub.0 to be input to the bit shift detector 32, that is, its phase is indeterminate, the above mentioned plurality of pre-detect-words are used and it is detected which coincides with the pattern of the synchronization among these patterns, so that the bit shift value of the synchronization SY.sub.0 from its correct bit position can be detected.
Thus, in the variable shift register 33 and the variable shift register 34, the supplied synchronization SY and identification code ID are changed from their break-points to correct bit positions. Then, the synchronization SY and identification code ID in the correct bit positions from the variable shift register 33 and the variable shift register 34 are respectively output to a synchronization/ID comparator 70.
Specifically explaining the above description, the synchronization SY of 0 to 15 bits from the variable shift register 33 is sent to a coincidence detector 71. The identification code ID of 16 to 39 bits is sent to a coincidence detector 73. The synchronization SY of 0 to 15 bits from the shift register 34 is supplied to a coincidence detector 72. The identification code ID of 16 to 39 bits is supplied to the coincidence detector 73.
In the coincidence detector 71, whether the data of synchronization SY of 16 bits after one synchronizing block is delayed coincides with a preset synchronizing word of 16 bits or not is detected. In the coincidence detector 72, whether the data of synchronization SY of 16 bits before one synchronizing block has not been yet delayed coincides with the above described synchronizing word of 16 bits or not is detected.
Further, in the coincidence detector 73, whether the data of identification code ID of 24 bits before one synchronizing block is not delayed coincides with the data of identification code ID of 24 bits after one synchronizing block is delayed or not is detected.
Outputs from the three coincidence detectors 71, 72 and 73 are input to an AND circuit 74, from which a synchronizing pulse is output when signals from the three coincidence detectors 71, 72 and 73 coincide together.
In this manner, the synchronization detector 58 detects a synchronization by employing the synchronizations and identification codes ID of the two synchronizing blocks.
As described above, since the eight kinds of pre-detect-words used in the bit shift detector 32 have 4 bits respectively, a hamming distance between any two among them is located within a range of 1 to 4. Therefore, if a decoding error of only one bit is generated in the synchronization data based on which the pre-detect-words are formed, the pattern of the synchronization data may possibly be different from the pattern of a correct pre-detect-word and coincide with the pattern of a different pre-detect-word. For example, when `0` is mistaken for the last `1` in `0111` of PHASE 0, PHASE 0 has the same value as `0110` of PHASE 7.
Therefore, in the case of a conventional bit shift detector, when a decoding error of not smaller than one bit is generated in the synchronization data, a bit shift value cannot be assuredly detected.